1. Field of the Invention
The invention, in general, relates to switching arrangements for logic circuits clocked at a very high frequency and to methods of clocking these logic circuits. More particularly, the invention relates to sequential circuits for integrated circuits which operate at very high clock frequencies.
2. The Prior Art
A known principle of structuring clocked logic circuits or sequential circuits of the kind depicted in FIG. 1 consists of connecting the data outputs of storage units or registers which are synchronously controlled by a clock, to the inputs of blocks of gates (a term which in the present context is intended also to include inverters) and of connecting, in turn, the outputs of the logic circuits to the input of registers, and so forth. Finite state machines as well as synchronously clocked data flow machines often make use of this principle. In such an arrangement, a subsequent register may be wholly or partially identical to the preceding one, so that cyclic feedbacks are generated.
The shorter the maximum time delay of a pass from a register through the signal path of the logic block to another register, the higher may be the selected clock rate and, hence, the processing power of such a clocked circuit. The maximum time delay of a clock cycle consists of the maximum duration of the signal passage through the block in the least favorable case (on the critical path) as well as the maximum time delays and, optionally, the necessary lead times of the registers utilized.
In circuits of this kind, the registers are necessary for interrupting the signal flow until all output signals of the logic circuit, which may obviously be subject to different time delays in the various paths, are valid and which at this instant store the signal for further transmission.
In simple logic functions of short signal passages through a given path of the block the maximum time delay for a clock cycle is essentially defined by the time delays of the registers. For that reason, a number of circuits seeking to reduce the time delay of registers have been developed (for instance U.S. Pat. No. 4,057,741).
It is, therefore, an object of the present invention to provide clocked circuits of very low time delays or very high data throughput.
It is a further object to provide logic circuits clocked at a high frequency and which require no registers for clocking the signal passage.
In accordance with a currently preferred embodiment this clocking is achieved by connecting at the output of a gate of the logic circuit an additional current source, hereinafter sometimes referred to as xe2x80x9cclocked current sourcexe2x80x9d, in parallel to the output of the corresponding gate. The output current of the additional current source is controlled by the frequency of a clock. The gate has one output and, in a generalized case, N inputs.